1. Field of the Invention
This document relates to a plasma display apparatus, and more particularly, to a plasma display apparatus for reducing heat generated in a data driver for supplying a driving voltage to an address electrode formed on a plasma display panel when driving the plasma display apparatus, and a driving method of the same.
2. Description of the Background Art
Generally, a plasma display panel comprises a front panel and a rear panel. Barrier ribs formed between the front panel and the rear panel form discharge cells. Each of the discharge cells is filled with an inert gas containing a main discharge gas such as neon (Ne), helium (He) or a Ne—He gas mixture and a small amount of xenon (Xe) The plurality of discharge cells forms one pixel. For example, red, green and blue discharge cells form one pixel.
When the plasma display panel is discharged by a high frequency voltage, the inert gas generates vacuum ultraviolet rays and the vacuum ultraviolet rays excite phosphors formed between the barrier ribs. As a result, an image is displayed on the plasma display panel. Since the above-described plasma display panel can be manufactured to be thin and light, the plasma display panel has been considered as a next generation display apparatus.
A plurality of electrodes, for example, a scan electrode, a sustain electrode and an address electrode are formed on the plasma display panel. A predetermined driving voltage is supplied to the plurality of electrodes to generate a discharge, thereby displaying the image on the plasma display panel. A drive integrated circuit (IC) is connected to each of the plurality of electrodes for supplying the driving voltage to the plurality of electrodes.
For example, a data drive IC is connected to the address electrode of the plurality of electrodes and a scan drive IC is connected to the scan electrode.
A plasma display apparatus comprises the plasma display panel on which the plurality of electrodes are formed, and the drive ICs for supplying the predetermined driving voltage to the plurality of electrodes of the plasma display panel.
A structure of the plasma display apparatus comprising the related art data drive IC for supplying the predetermined driving voltage to the address electrode of the plasma display panel will be described with reference to FIG. 1.
FIG. 1 shows a structure of a plasma display apparatus comprising a related art data drive IC.
As shown in FIG. 1, the plasma display apparatus comprises top switches Qt1, Qt2 and Qt3 and bottom switches Qb1, Qb2 and Qb3 connected in series between a data voltage source (not shown) for supplying a data voltage Vd and a ground voltage source (not shown) for supplying a ground level voltage GND.
A plurality of address electrodes X are connected between the top switches Qt1, Qt2 and Qt3 and the bottom switches Qb1, Qb2 and Qb3.
Each of the top switches Qt1, Qt2 and Qt3 and each of the bottom switches Qb1, Qb2 and Qb3 form a data drive IC. In other words, the top switch Qt1 and the bottom switch Qb1 form a data drive IC 100. The data drive IC 100 is connected to an address electrode Xa of the plurality of address electrodes X.
In the same manner as the data drive IC 100, the data drive ICs 101 and 102 are connected to address electrodes Xb and Xc, respectively.
Although three data drive ICs are shown in FIG. 1, the number of the data drive ICs may be variably changed depending on the number of address electrodes X.
An operation of the plasma display apparatus will be described with reference to FIG. 2.
FIG. 2 shows an operation timing for explaining an operation of the related art plasma display apparatus.
As shown in FIG. 2, when the top switch Qt1 of the data drive IC 100 is turned on in an address period, the data voltage Vd from the data voltage source (not shown) is supplied to the address electrode Xa through the top switch Qt1. Thus, as shown in FIG. 2, a voltage of the address electrode Xa rises up to the data voltage Vd, and then is maintained at the data voltage Vd.
When the top switch Qt1 of the data drive IC 100 is turned off and the bottom switch Qb1 is turned on, a voltage of the address electrode Xa falls to the ground level voltage GND. That is, a data pulse of the data voltage Vd is supplied to the address electrode Xa by alternately operating the top switch Qt1 and the bottom switch Qb1.
Switching operations for supplying a data pulse of each of the data drive ICs 101 and 102 are the same as the data drive IC 100.
Heat of a relatively high temperature is generated in the switches of each of the data drive ICs shown in FIG. 1 in the related art plasma display apparatus operated as described above.
For example, suppose that the data voltage Vd supplied from the data voltage source is 60 V and resistance of each of the top switches Qt1, Qt2 and Qt3 is R.
When the data drive IC 100 supplies the data voltage Vd to the address electrode Xa, a current flowing in the top switch Qt1 and a power consumed in the top switch Qt1 are represented by the following Equation 1.i=60V/R W=i×60V  [Equation 1]
In Equation 1, i denotes a current following in the top switch Qt1. W denotes a power consumed in the top switch Qt1.
As shown in the above Equation 1, when driving the data drive IC 100, the top switch Qt1 consumes a power corresponding to (i×60V). At this time, the heat is generated in the top switch Qt1 in proportion to the consumption power W. For example, supposing that a resistance of the top switch Qt1 is 30Ω, heat corresponding to a power of 120 W [(60/30)×60] is generated in the top switch Qt1.
Heat generated in each of the top switches Qt1, Qt2 and Qt3 is generated in each of the bottom switches Qb1, Qb2 and Qb3.
In particular, when image data is a specific pattern in which logic values 1 and 0 are repeated, heat of a considerably high temperature is generated in the switches of the data drive ICs, thereby burning the switches.
For example, when the number of discharge cells disposed on the address electrode Xa is 200 and the data voltage Vd is supplied to every other discharge cell of 200 discharge cells, heat corresponding to a maximum power of 12,000 W [(60/30)×60×100] is generated in the top switch Qt1 during an address period of a subfield.